The present invention relates to a semiconductor integrated circuit device and, more particularly, to a process for fabricating a semiconductor integrated circuit device which has a junction of a semiconductor region that is prevented from being destroyed.
In accordance with increasing integration of semiconductor devices such as IC's or LSI's in recent years, the element of these devices are made finer and finer. In the MOS type semiconductor device, the MOSFET (i.e., Metal Oxide Semiconductor Field Effect Transistor) has been scaled down, i.e., has its channel shortened. In accordance with this shortened channel, the semiconductor region (e.g., source or drain regions) of the element has its junction depth decreased to about 0.2 to 0.4 microns.
The semiconductor region is connected with aluminum used as a wiring layer. The heat treatment for establishing ohmic contact between the aluminum and the semiconductor region (Si) causes the so-called "alloy spike", in which the aluminum sinters into the substrate. When this alloy spike reaches the PN junction, this junction is short-circuited, or leakage current increases. As a result, the element is made less reliable. Thus, in the recent MOSFET which has its junction depth reduced year by year, as has been described above, a variety of trials have been made to suppress or prevent the junction destruction due to the alloy spike. One of the proposed methods is that the junction depth at the contact hole portion is locally enlarged by diffusing an impurity into the semiconductor region of the same conductivity type through contact holes. This method is simple, requiring only one step, and is effective.
This method is disclosed, for example, in the "Special Issue of Nikkei Electronics Microdevices", pp. 122, which issued on Aug. 23, 1983 by Nikkei McGraw Hill Co., Ltd. (published in Japan).
According to our investigations, in case the aforementioned method is applied as it is to such a semiconductor device (such as a CMOS device having P-channel MOSFETs and N-channel MOSFETs) that has a P-type semiconductor region and an N-type semiconductor region, the large number of steps for fabricating the CMOS device is further increased.